1. Field of the Invention
The present invention relates to a display device, a data driver IC, a gate driver IC and a scan line driving circuitry, in particular, a method of driving a large-size and high-resolution display panel.
2. Description of the Related Art
In recent years, display panel devices have become widely used in various electronic devices that require lower operating voltage, lower power consumption, and reduced size and weight. In particular, liquid crystal display devices, which are advantageous in terms of reduced power consumption, weight and size, compared to other display devices, have been adopted as display devices in various electronic appliances, such as televisions and personal computer monitors.
One typical liquid-crystal display device is the active matrix liquid crystal display device (AMLCD), which incorporates active elements such as TFT (Thin Film Transistor) in pixels. An active matrix liquid crystal display panel is typically composed of a set of data lines arranged in a column direction and a set of scan lines arranged in a row direction, and pixels including TFT disposed at respective intersections of the data lines and the scan lines. The data lines are driven by a data line driver, and the scan lines are driven by a scan line driver.
Recent requirements imposed on the liquid crystal display device include larger viewing area size and higher resolution. However, larger viewing area size and higher resolution undesirably causes variations in the pixel brightness depending on the positions on the liquid crystal display panel, since larger viewing area size and higher resolution enhance delays of the signals fed to pixels located away from the data line driver and the scan line driver, due to the capacitance and resistance of the data lines and the scan lines. Especially, one issue is the difference in brightness and contrast between the pixels located close to the data line driver and the scan line driver and the pixels located away from the data line driver and the scan line driver, which causes deformation of a displayed image.
Japanese Laid Open Patent Application No. 2005-004205 discloses a liquid crystal display device configured to avoid deterioration of display images due to the signal delay on the scan lines, which controls the timing of outputting display signals from the data line driver, and thereby applies the display signals and the associate scan signal outputted from the scan line driver to the associated pixels substantially at the same time.
FIG. 6 is a block diagram of the liquid crystal display device disclosed in the above-mentioned patent application, which is denoted by the numeral 100. The liquid crystal display device 100 is composed of a liquid crystal display panel 11, a data line driving circuitry 12 and a scan line driving circuitry 13. Provided on the liquid crystal display panel 11 are a plurality of data lines X1 to Xm (m is a natural number of 2 or more), a plurality of scan lines Y1 to Yn (n is a natural number of 2 or more), pixels P11 to Pmn each including a TFT 11c. It should be noted that FIG. 6 shows only four pixels P11, P1n, Pm1 and Pmn for simplicity of the figure. The data lines X1 to Xm are arranged to extend in the column direction, and the scan lines Y1 to Yn are arranged to extend in the row direction. The pixels P11 to Pmn are disposed at respective intersections of the data lines X1 to Xm and the scan lines Y1 to Yn. The gate electrodes of the TFTs 11c within the pixels P11 to Pmn are connected to the scan lines Y1 to Yn on nodes 1511 to 15mn, respectively, and the drain electrodes are connected to the data lines X1 to Xm on nodes 1411 to 14mn.
The liquid crystal display panel 11 additionally includes an output instruction line 17 arranged in parallel to the scan lines Y1 to Yn. As will be described later, the output instruction line 17 is used to control timings of driving the data lines X1 to Xm.
The data line driving circuitry 12 is provided with a timing controller 16 and data driver ICs 121 to 12p used to output display signals onto the data lines X1 to Xm. The data driver ICs 121 to 12p receive an output instruction signal TP from the timing controller 16 through the output instruction line 17, and the output timings of the data drive signals onto the data lines X1 to Xm are controlled in response to the output instruction signal TP. Specifically, the output instruction signal TP is delayed by the output instruction line 17 due to the capacitance and resistance thereof, and this allows the data driver ICs 121 to 12p to receive the output instruction signal TP at delayed timings depending on the distance from the scan line driving circuitry 13. Therefore, the liquid crystal display device 100 effectively reduces the timing lag between the display signals and the scan signals at positions away from the scan line driving circuitry 13.
This conventional technique, however, does not sufficiently deal with the delay of the display signals and the waveform distortion of the scan signals; this conventional technique only addresses dealing with the delay of the scan signals.
Specifically, as shown in FIG. 7A, the capacitance and resistance of the output instruction line 17 causes delay and waveform distortion of the output instruction signal TP within the conventional liquid crystal display device, and therefore, the driver ICs 121 to 12p receives the output instruction signal TP at different timings; hereinafter the output instruction signal TP received by the driver IC 12j is referred to as the output instruction signal TPj to clarify the timing of the reception. After the waveform reproduction within the respective driver ICs 12, the output instruction signals TP1 to TPp indicate different output timings of the display signals. This allows a display signal fed to a pixel located away from the scan line driving circuitry 13 (for example, the pixels Pm1) to be delayed with respect to a display signal fed to a pixel located close to the scan line driving circuitry 13 (for example, the pixels P11).
This conventional display device, however, does not deal with the waveform distortion of the scan signals due to the capacitance and resistance of the scan lines Y1 to Yn. In the conventional display device, the waveform distortion of the scan signals undesirably reduces “effective” pulse widths of the scan signals, since the scan signals are generated to have a constant pulse width. In order to sufficiently write a display signal into a desired pixel, the gate of the TFT within the pixel is activated by the scan signal with a voltage level sufficiently higher than the threshold voltage Vth1 of the TFT, (typically higher than the average Vth2 of the “low” and “high” levels). Undesirably, the waveform distortion of the scan signals reduces the duration during which the scan signals have a voltage level sufficiently higher than the threshold voltage Vth1, that is, the “effective” pulse of the scan signals. Specifically, as shown in FIG. 7B, the “effective” pulse width Td2 of the scan signal at the node 15p1 located farthest from the scan line driver 13 is narrower than the “effective” pulse width Tc2 of the scan signal at the note 1511 located closest to the scan line driving circuitry 13. This undesirably reduces the duration during which the display signal can be written into the associated pixel. Therefore, the conventional display device actually suffers from a problem that the contrast of the pixel located farthest from the scan line driver 13 (for example, the pixel Pm1) is lower than that of the pixel located closest to the scan line driver 13 (for example, P11).
Additionally, as shown in FIG. 8, the pulse width of the display signals which are output from the data drivers IC121 to 12p to the pixels P located further from the data line driver 12 is enlarged and delayed, and the output timings of the scan signals are not controlled depending on the distances between the data line driver 12 and the pixels P.
Such situation undesirably increases the lag between the timings of feeding the display signal and turning on the TFT with respect to a pixel away from the data line driving circuitry 12, reducing the brightness of the pixel.
In connection with the control of the pulse width of the scan signals, Japanese Laid Open Patent Application No. 2004-126581 describes a display device including a signal control unit which increases pulse widths of scan signals as the increase in the distance between the pixels and the data line driver. However, this display device does not achieve “dynamic control” of the output timings and pulse widths of the scan signals. The display device described in this patent application controls the pulse widths of the scan signals by a logic calculation or by using an RC circuit in which a resistance of a resistor is variable. Unfortunately, the logic calculation and the use of the RC circuit does not deal with the variations in the capacitance and resistance of the data lines from panel to panel, temperature dependence of the capacitance and resistance, and different deterioration rates of the panels.
As mentioned above, the conventional techniques suffer from the difficulty in the improvement of the rightness evenness (or the contrast uniformity) of the liquid crystal display panel due to the capacitance and resistance of the data lines and the scan lines.